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An Analytical And Numerical Model For Design Of Non- Uniformly Powered Silicon Chips Based On Both Thermal And Device Clock Performance

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An Analytical And Numerical Model For Design Of Non- Uniformly Powered Silicon Chips Based On Both Thermal And Device Clock Performance

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Title: An Analytical And Numerical Model For Design Of Non- Uniformly Powered Silicon Chips Based On Both Thermal And Device Clock Performance
Author: Kaisare, Abhijit D.
Abstract: Silicon chips continue to grow in capabilities, complexity and performance. Silicon chips typically integrate functional components such as logic and level two (L2) cache memory in their architecture. This functional integration of logic and memory results in improved performance of the chip. However, the integration also introduces a layer of complexity in the thermal design and management of silicon chips. As a direct result of functional integration, the power map on a silicon chip is typically highly non-uniform and the assumption of a uniform heat flux across the chip surface has been shown to be invalid post Pentium II architecture. The active side of the silicon chip is divided into several functional blocks with distinct power assigned to each functional block. Current research is focusing on microprocessor as a leading example but the work applies equally to other applications where silicon chips demonstrate non-uniformity. For instance graphic chips can exhibit non-uniformity so can ASICs. Initially, a numerical model is developed to minimize the on-die temperature of the package by optimizing the distribution of the non-uniformly powered functional blocks with different power matrices. In order to model the non-uniformly power dissipation on the silicon chip, the chip surface area is divided into different cases such as 3 x 3, 4 x 4, 8 x 8, 10 x 10 etc. of power matrix with a matrix space representing a distinct functional block with a constant heat flux. Finally, using a FEM code, an optimization of the positioning of the functional blocks relative to each other is carried out in order to minimize the junction temperature Tj (Maximum temperature on die). The best possible Tjmax reduction could thus be found. Based on the data derived from numerical model, for different power matrices, trend for the data is evaluated which helps to draw design guideline for a typical die configuration (i.e. 30 x 30). This is followed with a development of an analytical approach to temperature distribution of a first level package with a non-uniformly powered die which is carried for the first time. Previously developed analytical model [18] for two layer bodies is extended to this typical package which is a multilayer body. The solution is to begin by designating each surface heat flux as a volumetric heat source. An inverse methodology is applied to solve the equations for various surfaces to calculate maximum junction temperature for given multilayer body. Finally validation of the analytical solution is carried out using developed numerical model. In the end, a multi-objective optimization is carried out embedding developed numerical model into silicon floor plan to developed compact model satisfying both electrical and thermal performance. Recommendations are provided for an architecture design regarding maximum separation of functional block with minimum on-die temperature. The commercial finite element code ANSYS® is used in this study.
URI: http://hdl.handle.net/10106/736
Date: 2008-04-22

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