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Dynamic Thermal Management Of Multi Core Processors Using Core Hopping

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Dynamic Thermal Management Of Multi Core Processors Using Core Hopping

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Title: Dynamic Thermal Management Of Multi Core Processors Using Core Hopping
Author: Raghu, Avinash
Abstract: Multi core processors are the order of the day today. The demand for greater levels of performance and the consequent increase in design complexity have rendered the single core processor obsolete and resulted in more cores being put onto a single chip. Processors incorporating more than 4 cores on a chip are dubbed many core processors. This, while improving performance, has lead to increased power densities. Also, the power distribution across the die surface is not uniform. These factors together, result in heat being concentrated at specific points on the die surface, called `hot spots'.The increase in die temperature results in reduced performance and reliability and increased leakage currents and cooling costs. Existing cooling methodologies such as heat sinks and fans are hard pressed to alleviate the high temperatures associated with current generation multi core processors and with the inevitable increase in the number of cores in future, the feasibility and practicality of using these conventional techniques alone, comes into question. Dynamic Thermal Management Techniques such as Dynamic Voltage and Frequency Scaling are more or less successful in containing die temperature below a certain threshold but involve some throttling to lower power consumption, resulting in performance degradation. Spreading of activity across a many-core chip is increasingly being looked upon as a way to contain chip temperatures without degrading performance.In this study, an attempt to analyze the impact on temperature by performing power migration is made. It seeks to examine the possibility of increasing the number of active cores at any time, thereby further improving performance, while using power migration to maintain uniform power distribution and minimize overall temperature across the chip.
URI: http://hdl.handle.net/10106/4965
Date: 2010-07-19
External Link: https://www.uta.edu/ra/real/editprofile.php?onlyview=1&pid=4

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