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Characterization Of Thermal Challenges In Electronics : Leakage Current, Co-architectural Design And Rack Level Cooling

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Characterization Of Thermal Challenges In Electronics : Leakage Current, Co-architectural Design And Rack Level Cooling

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Title: Characterization Of Thermal Challenges In Electronics : Leakage Current, Co-architectural Design And Rack Level Cooling
Author: Raju, Uthaman
Abstract: ABSTRACTCHARACTERIZATION OF THERMAL CHALLENGES IN ELECTRONICS: LEAKAGE CURRENT, CO-ARCHITECTURAL DESIGN AND RACK LEVEL COOLING Uthaman Raju, M.SThe University of Texas at Arlington, 2008Faculty Mentor: Dereje AgonaferSince the advent of transistors and integrated circuits the complexity and functionality of the electronic products has gone up. In line with this, the scaling of the products is catching up at all levels of packaging. Current electronics era is driven by a mantra - "Miniaturization". Recently the number of transistors on high end microprocessor has exceeded a billon mark. The design at board level becomes sophisticated to meet the growing demands. All of these lead to thermal and reliability challenges. A good thermal design is one which makes sure that the chip is operating at its rated frequency or speed while maintaining the junction temperature within permissible limits. Due to miniaturization the device dimensions shrink leading to various problems at device level like leakage current, hotspots, etc., these problems at device level add up and in turn creates thermal issues at system level. Owing to time to market requirements, CFD analysis allows to complete thermal optimization long before the product test can be made available bringing about financial benefits and timely engineering support during product development. Thus thermal management at various level of electronics design becomes inevitable. In broad view thermal issues in electronics field is no longer an independent issue, it's ought to be multidisciplinary one. In this study device level issues like effect of gate oxide thickness on leakage current and co-architectural design of microprocessors is discussed. It is followed by system level thermal analysis of a telecommunication cabinet. Part-1 of the thesis addresses a device level issue, "Static Power Consumption - Silicon on Insulator Metal Oxide Semiconductor Field Effect Transistor". The static power consumption due to leakage current plays a significant part in semiconductor devices, as the device dimensions continue to shrink. Low power dissipation is one of the critical factors needed to achieve high performance in a chip. New methods are continuously being implemented for reduction of leakage current in deep sub micron ultra thin SOI MOSFET using device simulator tools. In this paper, an 18nm gate length ultra thin SOI MOSFET is simulated for different silicon body thicknesses and the leakage current is determined by using the device simulator, MEDICITM. It is demonstrated that MEDICITM device simulations is a good tool that can effectively be used for ultra thin SOI MOSFET devices to study the effect of design parameters on the leakage current.Ultra thin SOI MOSFET with 18nm gate length of different Silicon body thickness is simulated and the leakage current as determined by using MEDICITM shows that the leakage current decreases by 10-15% as the silicon body thickness reduces by 2 nm.Part-2 of the thesis again focuses on a device level issue, "Multi-Objective optimization entailing computer architecture and thermal design for non-uniformly powered microprocessors". Microprocessors continue to grow in capabilities, complexity and performance. Microprocessors typically integrate functional components such as logic and level two (L2) cache memory in their architecture. This functional integration of logic and memory results in improved performance of the microprocessor. However, the integration also introduces a layer of complexity in the thermal design and management of microprocessors. As a direct result of functional integration, the power map on a microprocessor is typically highly non-uniform and the assumption of a uniform heat flux across the chip surface has been shown to be invalid post Pentium II architecture. The active side of the die is divided into several functional blocks with distinct power assigned to each functional block. A lot of work has been done addressing this issue with a need of thermally aware computer architecture with a concurrent design approach based on thermal and device clock performance. Previous work has been done to minimize the thermal resistance of the package by optimizing the distribution of the non-uniform powered functional blocks with different power matrices. The study also provided design guidelines to minimize thermal resistance for any number of functional blocks for a given non-uniformly powered microprocessor. This analysis, however, had no constraints placed on the redistribution of functional blocks regarding the total wiring length of a particular configuration of functional blocks to satisfy electrical timing and computational performance requirements.In this study, numerical model is developed that utilizes muti-objective optimization consists of redistribution of functional blocks to both improve device performance and thermal performance. Previously developed design guideline for thermal optimization is used as a base line case. This baseline case will be embedded into computer architecture (floor Plan) to developed numerical model satisfying both electrical and thermal performance. Constraints for the electrical optimization will include the total wiring length of a particular configuration of functional blocks. Once positioning of the functional blocks is done, thermal and electrical optimization of these non-uniformly powered functional blocks will be carried out simultaneously. This process will be repeated until you get both improved device performance and thermal performance for the non-uniformly powered microprocessor. Finally recommendation will be provided for an architecture design considering both the electrical constraint (total wiring length) and minimum thermal resistance there by improving the performance.Part- 3 of the thesis deals with system level issue, "Rack Level Cooling". Computational Fluid Dynamics (CFD) is an integral part in the development of new products. A telecommunication cabinet has many components; therefore before the cabinet is manufactured it is necessary to know the thermal stability of the cabinet. It is extremely ineffective both in time and cost to build prototypes and test them (build and break approach). A CFD tool comes in handy for these kinds of problems where in lots of configurations can be modeled and tested in short periods of time. Based on the CFD results, a prototype cabinet is built and tested experimentally. Thus CFD tool allows for significant savings in both development and production. The development savings are realized by not having to physically build and test multiple configurations and the production savings are realized from cost reduction in the design.This paper deals with design and thermal analysis of a Commscope telecommunication cabinet, RBA48. This cabinet is completely sealed and is cooled by Heat Exchangers (HX) and TEC modules. This kind of cooling technology is first tried in this family of cabinets by Commscope, hence the different design configurations needs to be tested for thermal stability. The analysis of RBA48 concentrates on 1. The optimum door opening for the TEC modules2. Selection of HX fans - Outer loop fans3. Position of Bay Fans in the Bay Fan Tray.The CFD code Flotherm by Mentor Graphics is used for the analysis
URI: http://hdl.handle.net/10106/1858
Date: 2009-09-16
External Link: http://www.uta.edu/ra/real/editprofile.php?onlyview=1&pid=4

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