Issues In Front-end Engineering Of CMOS Nanoelectronics

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Issues In Front-end Engineering Of CMOS Nanoelectronics

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Title: Issues In Front-end Engineering Of CMOS Nanoelectronics
Author: Yang, Xiaolong
Abstract: Several issues exist in current CMOS front-end engineering such as interfacial layer formation at high-k/Si interface, high metal/Si contact resistance in source and drain regions, and absence of a quantitative model for silicon-germanium alloy growth. In this dissertation, monolayer Se passivation is employed to create a Si (100) surface free of dangling bonds. Since dangling bonds are the origins of surface reaction sites and surface states, interfacial layer formation at high-k/Si interface can be suppressed and metal/Si contact resistance can be lowered by Se passivation. Firstly, results on interface engineering between HfO2 and n-type Si (100) with Se passivation are reported. HfO2 on Se-passivated sample by dry oxidation at 300°C shows much improved properties: a smaller EOT (equivalent oxide thickness) 31 Å compared with EOT 65 Å for control sample, and a smaller leakage current with about 2 order of magnitude lowering. These results indicate Se passivation can effectively suppress the interfacial layer formation at the HfO2/Si interface and reduce the gate leakage current. Secondly, experimental results for Ti/n-type Se-passivated Si (100) contacts are presented. The sheet resistance of Se-passivated 10 19 cm-3 doped n-type Si (100) shows a 30% reduction as compared with control (non-passivated) samples. The extracted contact resistance decreases by about one order of magnitude. Up to 29 times reduction in contact resistivity is achieved by Se passivation on heavily-doped n-type SOI substrates. Finally, a kinetic model is proposed for Si1-xGex growth from SiH4 and GeH4 by chemical vapor deposition (CVD). Growth behaviors like growth rate and Ge content are discussed by considering both the heterogeneous and homogenous reactions. The model agrees well with the experimental data.
Date: 2007-08-23
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